In a process of designing a semiconductor integrated circuit, an Engineering Change Order (ECO) may be executed to wirings because of a logic change. Conventionally, a dummy wiring is arranged after a basic cell and a signal wiring are arranged in a chip.
However, in a conventional automatic layout and wiring technique, the layout of the basic cell and the signal wiring is more efficiently performed, in other words, the layout described above is performed in order to reduce an ineffective region as much as possible. Therefore, the number of wirings and the wiring spot of the dummy wiring are limited. Accordingly, in the ECO of the wiring using the dummy wiring, an ECO might be caused in plural wiring layers, or a layout has to be re-designed from the beginning since the ECO using the dummy wiring cannot be executed. When an ECO is needed after the fabrication of a mask, the execution of the ECO for plural wiring layers leads to the increase in a number of corrected masks, with the result that a cost might be increased. When the layout is re-designed from the beginning, the time taken for the layout design is increased, which entails a problem of a prolonged design period and an increase in a design cost.